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? slos019e ? september 1988 ? revised february 2005 1 post office box 655303 ? dallas, texas 75265 extremely low offset voltage ...1 v max extremely low change on offset voltage with temperature . . . 0.003 v/ c typ low input offset current 500 pa max at t a = ? 55 c to 125 c a vd . . . 135 db min cmrr . . . 120 db min k svr ...110 db min single-supply operation common-mode input voltage range includes the negative rail no noise degradation with external capacitors connected to v dd ? description the tlc2652 and tlc2652a are high-precision chopper-stabilized operational amplifiers using texas instruments advanced lincmos ? pro- cess. this process, in conjunction with unique chopper-stabilization circuitry, produces opera- tional amplifiers whose performance matches or exceeds that of similar devices available today. chopper-stabilization techniques make possible extremely high dc precision by continuously nulling input offset voltage even during variations in temperature, time, common-mode voltage, and power supply voltage. in addition, low-frequency noise voltage is significantly reduced. this high precision, coupled with the extremely high input impedance of the cmos input stage, makes the tlc2652 and tlc2652a an ideal choice for low-level signal processing applications such as strain gauges, thermocouples, and other transducer amplifiers. for applications that require extremely low noise and higher usable bandwidth, use the tlc2654 or tlc2654a device, which has a chopping frequency of 10 khz. the tlc2652 and tlc2652a input common-mode range includes the negative rail, thereby providing superior performance in either single-supply or split-supply applications, even at power supply voltage levels as low as 1.9 v. two external capacitors are required for operation of the device; however, the on-chip chopper-control circuitry is transparent to the user. on devices in the 14-pin and 20-pin packages, the control circuitry is made accessible to allow the user the option of controlling the clock frequency with an external frequency source. in addition, the clock threshold level of the tlc2652 and tlc2652a requires no level shifting when used in the single-supply configuration with a normal cmos or ttl clock input. copyright ? 1988?2005, t exas instruments incorporated please be aware that an important notice concerning avail ability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. advanced lincmos is a trademark of texas instruments. 1 2 3 4 8 7 6 5 c xb v dd + out clamp d008, jg, or p package nc ? no internal connection 1 2 3 4 5 6 7 14 13 12 11 10 9 8 int/ext clk in clk out v dd + out clamp c return d014, j, or n package (top view) 3212019 910111213 4 5 6 7 8 18 17 16 15 14 clk out nc v dd + nc out fk package (top view) int/ext nc clamp clk in nc nc xa v c return xb v dd? v (top view) nc nc in ? nc in + c xb c xa nc in ? in + nc v dd ? c xa in ? in + v dd ?
? slos019e ? september 1988 ? revised february 2005 2 post office box 655303 ? dallas, texas 75265 description (continued) innovative circuit techniques are used on the tlc2652 and tlc2652a to allow exceptionally fast overload recovery time. if desired, an output clamp pin is available to reduce the recovery time even further. the device inputs and output are designed to withstand 100-ma surge currents without sustaining latch-up. additionally the tlc2652 and tlc2652a incorporate internal esd-protection circuits that prevent functional failures at voltages up to 2000 v as tested under mil-std-883c, method 3015.2; however, care should be exercised in handling these devices, as exposure to esd may result in degradation of the device parametric performance. the c-suffix devices are characterized for operation from 0 c to 70 c. the i-suffix devices are characterized for operation from ? 40 c to 85 c. the q-suffix devices are characterized for operation from ? 40 c to125 c. the m-suffix devices are characterized for operation over the full military temperature range of ? 55 c to125 c. available options (1) packaged devices v io max 8 pin 14 pin 20 pin chip form t a v io max at 25 c small outline (d008) ceramic dip (jg) plastic dip (p) small outline (d014) ceramic dip (j) plastic dip (n) chip carrier (fk) chip form (y) 0 c 1 v tlc2652ac-8d ? tlc2652acp tlc2652ac-14d ? tlc2652acn ? 0 c to 70 c 1 v 3 v tlc2652ac-8d tlc2652c-8d ? ? tlc2652acp tlc2652cp tlc2652ac-14d tlc2652c - 14d ? ? tlc2652acn tlc2652cn ? ? tlc2652y to 70 c 3 v tlc2652c-8d ? tlc2652cp tlc2652c - 14d ? tlc2652cn ? tlc2652y ?40 c 1 v tlc2652ai-8d ? tlc2652aip tlc2652ai-14d ? tlc2652ain ? ?40 c to 85 c 1 v 3 v tlc2652ai-8d tlc2652a-8d ? ? tlc2652aip tlc2652ip tlc2652ai-14d tlc2652i-14d ? ? tlc2652ain tlc2652in ? ? ? to 85 c 3 v tlc2652a-8d ? tlc2652ip tlc2652i-14d ? tlc2652in ? ? ?40 c ?40 c to 125 c 3.5 v tlc2652q-8d ? ? ? ? ? ? ? to 125 c 3.5 v tlc2652q-8d ? ? ? ? ? ? ? ?55 c to 3 v tlc2652am-8d tlc2652amjg tlc2652amp tlc2652am-14d tlc2652amj tlc2652amn tlc2652amfk ? to 125 c 3 v 3.5 v tlc2652am-8d tlc2652m-8d tlc2652amjg tlc2652mjg tlc2652amp tlc2652mp tlc2652am-14d tlc2652m-14d tlc2652amj tlc2652mj tlc2652amn tlc2652mn tlc2652amfk tlc2652mfk ? the d008 and d014 packages are available taped and reeled. add r suffix to the device type (e.g., tlc2652ac-8dr). chips are tes ted at 25 c. note (1): for the most current package and ordering information, see the package option addendum at the end of this document, or see the ti website at www.ti.com. functional block diagram clamp circuit clamp out c return v dd ? compensation- biasing circuit v dd + a b b a in + in ? c xa c xb external components null main + ? + ? ab distribution of tlc2652 input offset voltage percentage of units ? % v io ? input offset voltage ? v ?3 ?2 ?1 0 1 2 3 0 4 8 12 16 20 24 28 32 36 150 units tested from 1 wafer lot v dd = 5 v t a = 25 c n package c ic 5 4 2 3 6 7 8 pin numbers shown are for the d (14 pin), jg, and n packages.
? slos019e ? september 1988 ? revised february 2005 3 post office box 655303 ? dallas, texas 75265 tlc2652y chip information this chip, when properly assembled, displays characteristics similar to the tlc2652c. thermal compression or ultrasonic bonding may be used on the doped-aluminum bonding pads. chips may be mounted with conductive epoxy or a gold-silicon preform. bonding pad assignments chip thickness: 15 typical bonding pads: 4 4 minimum t j max = 150 c tolerances are 10%. all dimensions are in mils. pin (7) is internally connected to back side of chip. for the pinout, see the functional block diagram. 90 80 (13) (12) (11) (10) (9) (8) (1) (7) (5) (4) (2) (14)
? slos019e ? september 1988 ? revised february 2005 4 post office box 655303 ? dallas, texas 75265 absolute maximum ratings over operating free-air temperature range (unless otherwise noted) ? supply voltage v dd + (see note 1) 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . supply voltage v dd ? (see note 1) ?8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . differential input voltage, v id (see note 2) 16 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input voltage, v i (any input, see note 1) 8 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . voltage range on clk in and int/ext v dd ? to v dd ? + 5.2 v . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . input current, i i (each input) 5 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . output current, i o 50 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . duration of short-circuit current at (or below) 25 c (see note 3) unlimited . . . . . . . . . . . . . . . . . . . . . . . . . . . . . current into clk in and int/ext 5 ma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . continuous total dissipation see dissipation rating table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . operating free-air temperature range, t a : c suffix 0 c to 70 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i suffix ?40 c to 85 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . q suffix ?40 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . m suffix ?55 c to 125 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . storage temperature range ?65 c to 150 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . case temperature for 60 seconds: fk package 260 c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 10 seconds: d, n, or p package 260 c . . . . . . . . . . . . . lead temperature 1,6 mm (1/16 inch) from case for 60 seconds: j or jg package 300 c . . . . . . . . . . . . . . . . ? stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress ratings only, a nd functional operation of the device at these or any other conditions beyond those indicated under ?recommended operating conditi ons? is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. notes: 1. all voltage values, except differential voltages, are with respect to the midpoint between v dd + and v dd ? . 2. differential voltages are at in+ with respect to in ?. 3. the output may be shorted to either supply. temperature and/or supply voltages must be limited to ensure that the maximum dissipation rating is not exceeded. dissipation rating table package t a 25 c derating factor t a = 70 c t a = 85 c t a = 125 c package t a 25 c power rating derating factor above t a = 25 c t a = 70 c power rating t a = 85 c power rating t a = 125 c power rating d008 725 mv 5.8 mw/ c 464 mw 377 mw 145 mw d014 950 mv 7.6 mw/ c 608 mw 494 mw 190 mw fk 1375 mv 11.0 mw/ c 880 mw 715 mw 275 mw j 1375 mv 11.0 mw/ c 880 mw 715 mw 275 mw jg 1050 mv 8.4 mw/ c 672 mw 546 mw 210 mw n 1575 mv 12.6 mw/ c 1008 mw 819 mw 315 mw p 1000 mv 8.0 mw/ c 640 mw 520 mw 200 mw recommended operating conditions c suffix i suffix q suffix m suffix unit min max min max min max min max unit supply voltage, v dd 1.9 8 1.9 8 1.9 8 1.9 8 v common-mode input voltage, v ic v dd ? v dd + ? 1.9 v dd ? v dd + ? 1.9 v dd ? v dd + ? 1.9 v dd ? v dd + ? 1.9 v clock input voltage v dd ? v dd ? +5 v dd ? v dd ? +5 v dd ? v dd ? +5 v dd ? v dd ? +5 v operating free-air temperature, t a 0 70 ?40 85 ?40 125 ?55 125 c
? slos019e ? september 1988 ? revised february 2005 5 post office box 655303 ? dallas, texas 75265 electrical characteristics at specified free-air temperature, v dd = 5 v (unless otherwise noted) parameter test conditions t a ? tlc2652c tlc2652ac unit parameter test conditions t a ? min typ max min typ max unit v io input offset voltage 25 c 0.6 3 0.5 1 v v io input offset voltage full range 4.35 2.35 v vio temperature coefficient of full range 0.003 0.03 0.003 0.03 v/ c vio temperature coefficient of input offset voltage full range 0.003 0.03 0.003 0.03 v/ c input offset voltage long-term drift (see note 4) v ic = 0, r s = 50 ? 25 c 0.003 0.06 0.003 0.02 v/mo i io input offset current 25 c 2 60 2 60 pa i io input offset current full range 100 100 pa i ib input bias current 25 c 4 60 4 60 pa i ib input bias current full range 100 100 pa common-mode input voltage ?5 ?5 v icr common-mode input voltage range r s = 50 ? full range ?5 to ?5 to v v icr range r s = 50 ? ? c 4.7 4.8 4.7 4.8 v v om + maximum positive peak output voltage swing r l = 10 k ?, see note 5 full range 4.7 4.7 v v om ? maximum negative peak r l = 10 k ? c ?4.7 ?4.9 ?4.7 ?4.9 v v om ? maximum negative peak output voltage swing r l = 10 k ?, see note 5 full range ?4.7 ?4.7 v a vd large-signal differential v o = 4 v, r l = 10 k ? c 120 150 135 150 db a vd large-signal differential voltage amplification v o = 4 v, r l = 10 k ? full range 120 130 db f ch internal chopping frequency 25 c 450 450 hz clamp on-state current r l = 100 k ? c 25 25 a clamp on-state current r l = 100 k ? full range 25 25 a clamp off-state current v o = ? 4 v to 4 v 25 c 100 100 pa clamp off-state current v o = ? 4 v to 4 v full range 100 100 pa cmrr common-mode rejection v o = 0, v ic = v icr min, 25 c 120 140 120 140 db cmrr common-mode rejection ratio v o = 0, v ic = v icr min, r s = 50 ? full range 120 120 db k svr supply-voltage rejection ratio v dd = 1.9 v to 8 v, 25 c 110 135 110 135 db k svr supply-voltage rejection ratio ( ? v dd / ? v io ) v o = 0, r s = 50 ? full range 110 110 db i dd supply current 25 c 1.5 2.4 1.5 2.4 ma i dd supply current full range 2.5 2.5 ma ? full range is 0 to 70 c. notes: 4. typical values are based on the input of fset voltage shift observed through 168 hours of operating life test at t a = 150 c extrapolated at t a = 25 using the arrhenius equation and assuming an activation energy of 0.96 ev. 5. output clamp is not connected.
? slos019e ? september 1988 ? revised february 2005 6 post office box 655303 ? dallas, texas 75265 operating characteristics specified free-air temperature, v dd = 5 v parameter test t a ? tlc2652c tlc2652ac unit parameter test conditions t a ? min typ max min typ max unit sr + positive slew rate at unity gain v = 2.3 v, 25 c 2 2.8 2 2.8 v/ s sr + positive slew rate at unity gain v o = 2.3 v, r l = 10 k ? , full range 1.5 1.5 v/ s sr ? negative slew rate at unity gain o r l = 10 k ? , c l = 100 pf 25 c 2.3 3.1 2.3 3.1 v/ s sr ? negative slew rate at unity gain c l = 100 pf full range 1.8 1.8 v/ s v n equivalent input noise voltage f = 10 hz 25 c 94 94 140 nv/ hz v n equivalent input noise voltage (see note 6) f = 1 khz 25 c 23 23 35 nv/ hz v n(pp) peak-to-peak equivalent input f = 0 to 1 hz 25 c 0.8 0.8 v v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 10 hz 25 c 2.8 2.8 v i n equivalent input noise current f = 10 khz 25 c 0.004 0.004 fa/ hz f = 10 khz, gain-bandwidth product f = 10 khz, r l = 10 k ? , 25 c 1.9 1.9 mhz gain-bandwidth product r l = 10 k ? , c l = 100 pf 25 c 1.9 1.9 mhz m phase margin at unity gain r l = 10 k ? , c l = 100 pf 25 c 48 48 ? full range is 0 to 70 c. note 6: this parameter is tested on a sample basis for the tlc2652a. for other test requirements, please contact the factory. th is statement has no bearing on testing or nontesting of other parameters.
? slos019e ? september 1988 ? revised february 2005 7 post office box 655303 ? dallas, texas 75265 electrical characteristics at specified free-air temperature, v dd = 5 v (unless otherwise noted) parameter test conditions t a ? tlc2652i tlc2652ai unit parameter test conditions t a ? min typ max min typ max unit v io input offset voltage 25 c 0.6 3 0.5 1 v v io input offset voltage full range 4.95 2.95 v vio temperature coefficient of full range 0.003 0.03 0.003 0.03 v/ c vio temperature coefficient of input offset voltage full range 0.003 0.03 0.003 0.03 v/ c input offset voltage long-term drift (see note 4) v ic = 0, r s = 50 ? 25 c 0.003 0.06 0.003 0.02 v/mo i io input offset current 25 c 2 60 2 60 pa i io input offset current full range 150 150 pa i ib input bias current 25 c 4 60 4 60 pa i ib input bias current full range 150 150 pa common-mode input ?5 ?5 v icr common-mode input voltage range r s = 50 ? full range ?5 to ?5 to v v icr voltage range r s = 50 ? ? c 4.7 4.8 4.7 4.8 v v om + maximum positive peak output voltage swing r l = 10 k ?, see note 5 full range 4.7 4.7 v v om ? maximum negative peak r l = 10 k ? c ?4.7 ?4.9 ?4.7 ?4.9 v v om ? maximum negative peak output voltage swing r l = 10 k ?, see note 5 full range ?4.7 ?4.7 v a vd large-signal differential v o = 4 v, r l = 10 k ? c 120 150 135 150 db a vd large-signal differential voltage amplification v o = 4 v, r l = 10 k ? full range 120 125 db internal chopping frequency 25 c 450 450 hz clamp on-state current r l = 100 k ? c 25 25 a clamp on-state current r l = 100 k ? full range 25 25 a clamp off-state current v o = ? 4 v to 4 v 25 c 100 100 pa clamp off-state current v o = ? 4 v to 4 v full range 100 100 pa cmrr common-mode rejection v o = 0, v ic = v icr min, 25 c 120 140 120 140 db cmrr common-mode rejection ratio v o = 0, v ic = v icr min, r s = 50 ? full range 120 120 db k svr supply-voltage rejection v dd = 1.9 v to 8 v, 25 c 110 135 110 135 db k svr supply-voltage rejection ratio ( ? v dd / ? v io ) v o = 0, r s = 50 ? full range 110 110 db i dd supply current v o = 0, no load 25 c 1.5 2.4 1.5 2.4 ma i dd supply current v o = 0, no load full range 2.5 2.5 ma ? full range is ? 40 to 85 c. notes: 4. typical values are based on the input of fset voltage shift observed through 168 hours of operating life test at t a = 150 c extrapolated at t a = 25 using the arrhenius equation and assuming an activation energy of 0.96 ev. 5. output clamp is not connected.
? slos019e ? september 1988 ? revised february 2005 8 post office box 655303 ? dallas, texas 75265 operating characteristics at specified free-air temperature, v dd = 5 v parameter test t a ? tlc2652i tlc2652ai unit parameter test conditions t a ? min typ max min typ max unit sr + positive slew rate at unity gain v = 2.3 v, 25 c 2 2.8 2 2.8 v/ s sr + positive slew rate at unity gain v o = 2.3 v, r l = 10 k ? , full range 1.4 1.4 v/ s sr ? negative slew rate at unity gain o r l = 10 k ? , c l = 100 pf 25 c 2.3 3.1 2.3 3.1 v/ s sr ? negative slew rate at unity gain c l = 100 pf full range 1.7 1.7 v/ s v n equivalent input noise voltage f = 10 hz 25 c 94 94 140 nv/ hz v n equivalent input noise voltage (see note 6) f = 1 khz 25 c 23 23 35 nv/ hz v n(pp) peak-to-peak equivalent input f = 0 to 1 hz 25 c 0.8 0.8 v v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 10 hz 25 c 2.8 2.8 v i n equivalent input noise current f = 1 khz 25 c 0.004 0.004 pa/ hz f = 10 khz, gain-bandwidth product f = 10 khz, r l = 10 k ? , 25 c 1.9 1.9 mhz gain-bandwidth product r l = 10 k ? , c l = 100 pf 25 c 1.9 1.9 mhz m phase margin at unity gain r l = 10 k ? , c l = 100 pf 25 c 48 48 ? full range is ? 40 to 85 c. note 6: this parameter is tested on a sample basis for the tlc2652a. for other test requirements, please contact the factory. th is statement has no bearing on testing or nontesting of other parameters.
? slos019e ? september 1988 ? revised february 2005 9 post office box 655303 ? dallas, texas 75265 electrical characteristics at specified free-air temperature, v dd = 5 v (unless otherwise noted) parameter test conditions t a ? tlc2652q tlc2652m tlc2652am unit parameter test conditions t a ? min typ max min typ max unit v io input offset voltage 25 c 0.6 3.5 0.5 3 v v io input offset voltage (see note 7) full range 10 8 v vio temperature coefficient of full range 0.003 0.03 ? ? c vio temperature coefficient of input offset voltage full range 0.003 0.03 ? 0.003 0.03 ? v/ c input offset voltage long-term drift (see note 4) v ic = 0, r s = 50 ? 25 c 0.003 0.06 ? 0.003 0.02 ? v/mo i io input offset current 25 c 2 60 2 60 pa i io input offset current full range 500 500 pa i ib input bias current 25 c 4 60 4 60 pa i ib input bias current full range 500 500 pa common-mode input ?5 ?5 v icr common-mode input voltage range r s = 50 ? full range ?5 to ?5 to v v icr voltage range r s = 50 ? ? c 4.7 4.8 4.7 4.8 v v om + maximum positive peak output voltage swing r l = 10 k ?, see note 5 full range 4.7 4.7 v v om ? maximum negative peak r l = 10 k ? c ?4.7 ?4.9 ?4.7 ?4.9 v v om ? maximum negative peak output voltage swing r l = 10 k ?, see note 5 full range ?4.7 ?4.7 v a vd large-signal differential v o = 4 v, r l = 10 k ? c 120 150 135 150 db a vd large-signal differential voltage amplification v o = 4 v, r l = 10 k ? full range 120 120 db f ch internal chopping frequency 25 c 450 450 hz clamp on-state current v o = ? 5 v to 5 v 25 c 25 25 a clamp on-state current v o = ? 5 v to 5 v full range 25 25 a clamp off-state current r l = 100 k ? c 100 100 pa clamp off-state current r l = 100 k ? full range 500 500 pa cmrr common-mode rejection v o = 0, v ic = v icr min, 25 c 120 140 120 140 db cmrr common-mode rejection ratio v o = 0, v ic = v icr min, r s = 50 ? full range 120 120 db k svr supply-voltage rejection v dd = 1.9 v to 8 v, 25 c 110 135 110 135 db k svr supply-voltage rejection ratio ( ? v dd / ? v io ) v o = 0, r s = 50 ? full range 110 110 db i dd supply current v o = 0, no load 25 c 1.5 2.4 1.5 2.4 ma i dd supply current v o = 0, no load full range 2.5 2.5 ma ? on products compliant to mil-prf-38535, this parameter is not production tested. ? full range is ? 40 to 125 c for q suffix, ? 55 to 125 c for m suffix. notes: 4. typical values are based on the input of fset voltage shift observed through 168 hours of operating life test at t a = 150 c extrapolated at t a = 25 using the arrhenius equation and assuming an activation energy of 0.96 ev. 5. output clamp is not connected. 7. this parameter is not production tested. thermocouple effects preclude measurement of the actual v io of these devices in high speed automated testing. v io is measured to a limit determined by the test equipment capability at the temperature extremes. the test ensures that the stabilization circuitry is performing properly.
? slos019e ? september 1988 ? revised february 2005 10 post office box 655303 ? dallas, texas 75265 operating characteristics at specified free-air temperature, v dd = 5 v parameter test conditions t a ? tlc2652q tlc2652m tlc2652am unit a min typ max sr + positive slew rate at unity gain v = 2.3 v, 25 c 2 2.8 v/ s sr + positive slew rate at unity gain v o = 2.3 v, r l = 10 k ? , full range 1.3 v/ s sr ? negative slew rate at unity gain o r l = 10 k ? , c l = 100 pf 25 c 2.3 3.1 v/ s sr ? negative slew rate at unity gain c l = 100 pf full range 1.6 v/ s v n equivalent input noise voltage f = 10 hz 25 c 94 nv/ hz v n equivalent input noise voltage f = 1 khz 25 c 23 nv/ hz v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 1 hz 25 c 0.8 v v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 10 hz 25 c 2.8 v i n equivalent input noise current f = 1 khz 25 c 0.004 pa/ hz gain-bandwidth product f = 10 khz, r l = 10 k ? , c l = 100 pf 25 c 1.9 mhz m phase margin at unity gain r l = 10 k ? , c l = 100 pf 25 c 48 ? full range is ? 40 to 125 c for the q suffix, ? 55 to 125 c for the m suffix.
? slos019e ? september 1988 ? revised february 2005 11 post office box 655303 ? dallas, texas 75265 electrical characteristics at v dd = 5 v, t a = 25 c (unless otherwise noted) parameter test conditions tlc2652y unit parameter test conditions min typ max unit v io input offset voltage 0.6 3 v input offset voltage long-term drift (see note 4) v ic = 0, r s = 50 ? v/mo i io input offset current v ic = 0, r s = 50 ? 2 60 pa i ib input bias current 4 60 pa ?5 v icr common-mode input voltage range r s = 50 ? ?5 to v v icr common-mode input voltage range r s = 50 ? ?, see note 5 4.7 4.8 v v om ? maximum negative peak output voltage swing r l = 10 k ?, see note 5 ?4.7 ?4.9 v a vd large-signal differential voltage amplification v o = 4 v, r l = 10 k ? 120 150 db f ch internal chopping frequency 450 hz clamp on-state current r l = 100 k ? 25 a clamp off-state current v o = ? 4 v to 4 v 100 pa cmrr common-mode rejection ratio v o = 0, r s = 50 ? v ic = v icr min, 120 140 db k svr supply-voltage rejection ratio ( ? v dd / ? v io ) v dd = 1.9 v to 8 v, 110 135 db k svr supply-voltage rejection ratio ( ? v dd / ? v io ) r s = 50 ? v o = 0, 110 135 db i dd supply current v o = 0, no load 1.5 2.4 ma notes: 4. typical values are based on the input of fset voltage shift observed through 168 hours of operating life test at t a = 150 c extrapolated at t a = 25 using the arrhenius equation and assuming an activation energy of 0.96 ev. 5. output clamp is not connected. operating characteristics at v dd = 5 v, t a = 25 c parameter test conditions tlc2652y unit parameter test conditions min typ max unit sr + positive slew rate at unity gain v o = 2.3 v, r l = 10 k , 2 2.8 v/ s sr ? negative slew rate at unity gain v o = 2.3 v, c l = 100 pf r l = 10 k ? , 2.3 3.1 v/ s v n equivalent input noise voltage f = 10 hz 94 nv/ hz v n equivalent input noise voltage f = 1 khz 23 nv/ hz v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 1 hz 0.8 v v n(pp) peak-to-peak equivalent input noise voltage f = 0 to 10 hz 2.8 v i n equivalent input noise current f = 1 khz pa/ hz gain-bandwidth product f = 10 khz, c l = 100 pf r l = 10 k ? , 1.9 mhz m phase margin at unity gain r l = 10 k ? , c l = 100 pf 48
? slos019e ? september 1988 ? revised february 2005 12 post office box 655303 ? dallas, texas 75265 typical characteristics table of graphs figure v io normalized input offset voltage vs chopping frequency 1 vs common-mode input voltage 2 i ib input bias current vs common-mode input voltage vs chopping frequency 2 3 i ib input bias current vs chopping frequency vs free-air temperature 3 4 i io input offset current vs chopping frequency 5 i io input offset current vs chopping frequency vs free-air temperature 5 6 clamp current vs output voltage 7 v (opp) maximum peak-to-peak output voltage vs frequency 8 v om maximum peak output voltage vs output current 9, 10 v om maximum peak output voltage vs output current vs free-air temperature 9, 10 11, 12 a vd large-signal differential voltage amplification vs frequency 13 a vd large-signal differential voltage amplification vs frequency vs free-air temperature 13 14 chopping frequency vs supply voltage 15 chopping frequency vs supply voltage vs free-air temperature 15 16 i dd supply current vs supply voltage 17 i dd supply current vs supply voltage vs free-air temperature 17 18 i os short-circuit output current vs supply voltage 19 i os short-circuit output current vs supply voltage vs free-air temperature 19 20 sr slew rate vs supply voltage 21 sr slew rate vs supply voltage vs free-air temperature 21 22 voltage-follower pulse response small-signal 23 voltage-follower pulse response small-signal large-signal 23 24 v n(pp) peak-to-peak equivalent input noise voltage vs chopping frequency 25, 26 v n equivalent input noise voltage vs frequency 27 gain-bandwidth product vs supply voltage 28 gain-bandwidth product vs supply voltage vs free-air temperature 28 29 vs supply voltage 30 m phase margin vs supply voltage vs free-air temperature 30 31 m phase margin vs free-air temperature vs load capacitance 31 32 phase shift vs frequency 13
? slos019e ? september 1988 ? revised february 2005 13 post office box 655303 ? dallas, texas 75265 typical characteristics ? normalized input offset voltage vs chopping frequency ?10 0 10 20 30 40 50 60 70 100 1 k 10 k 100 k chopping frequency ? hz v dd = 5 v v ic = 0 t a = 25 c vio ? normalized input offset ? uv v io v figure 1 ?5 v ic ? common-mode input voltage ? v iib ? input bias current ? pa 10 5 0 01 15 20 input bias current vs common-mode input voltage 25 2345 i ib v dd = 5 v t a = 25 c ?4 ?3 ?2 ?1 figure 2 figure 3 chopping frequency ? hz 30 10 0 60 20 iib ? input bias current ? pa 50 40 70 input bias current vs chopping frequency 100 1 k 10 k 100 k ib i v dd = 5 v v ic = 0 t a = 25 c t a ? free-air temperature ? c 1 100 25 45 65 105 125 input bias current vs free-air temperature 85 10 v dd = 5 v v o = 0 v ic = 0 iib ? input bias current ? pa ib i figure 4 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 14 post office box 655303 ? dallas, texas 75265 typical characteristics ? input offset current vs chopping frequency chopping frequency ? hz 20 10 5 0 25 15 100 1 k 10 k 100 k iio ? input offset current ? pa i io v dd = 5 v v ic = 0 t a = 25 c figure 5 figure 6 iio ? input offset current ? pa i io t a ? free-air temperature ? c 6 4 2 0 25 45 65 85 8 input offset current vs free-air temperature 10 105 125 v dd = 5 v v ic = 0 |v o | ? output voltage ? v 1 na 100 pa 10 pa 1 pa 4 4.2 4.4 4.6 clamp current vs output voltage 4.8 5 100 na 10 na v dd = 5 v t a = 25 c negative clamp current 100 a 10 a 1 a positive clamp current |clamp current| figure 7 8 4 2 0 10 6 100 1 k 10 k 1 m vo(pp) ? maximum peak-to-peak output voltage ? v f ? frequency ? hz maximum peak-to-peak output voltage vs frequency v o(pp) v dd = 5 v r l = 10 k ? t a = 125 c t a = ? 55 c figure 8 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 15 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 9 |i o | ? output current ? ma 4.6 4.4 4.2 4 0 0.4 0.8 1.2 4.8 maximum peak output voltage vs output current 5 1.6 2 v dd = 5 v t a = 25 c v om + v om ? |vom| ? maximum peak output voltage ? v |v om figure 10 |i o | ? output current ? ma 7.1 6.9 6.7 0 0.4 0.8 1.2 7.3 maximum peak output voltage vs output current 7.5 1.6 2 v dd = 7.5 v t a = 25 c v om + v om ? |vom| ? maximum peak output voltage ? v |v om figure 11 t a ? free-air temperature ? c 0 ?75 0 25 50 2.5 maximum peak output voltage vs free-air temperature 5 75 100 125 v dd = 5 v r l = 10 k ? ?2.5 vom ? maximum peak output voltage ? v v om ?5 ?50 ?25 figure 12 vom ? maximum peak output voltage ? v 0 4 maximum peak output voltage vs free-air temperature 8 t a ? free-air temperature ? c ?75 0 25 50 75 100 125 v dd = 7.5 v r l = 10 k ? v om ?50 ?25 ?8 ?4 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 16 post office box 655303 ? dallas, texas 75265 typical characteristics ? 20 0 40 60 80 10 100 1 k 10 k 100 k f ? frequency ? hz large-signal differential voltage amplification and phase shift vs frequency 1 m 10 m 100 120 220 200 180 160 140 120 100 80 60 v dd = 5 v r l = 10 k ? c l = 100 pf t a = 25 c a vd ?20 ?40 phase shift avd ? large-signal differential c v dd = 7.5 v r l = 10 k ? v o = 4 v avd ? large-signal differential ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 17 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 15 |v dd | ? supply voltage ? v 480 460 440 420 012345 500 520 chopping frequency vs supply voltage 540 678 t a = 25 c chopping frequency ? khz figure 16 ?50 ?25 t a ? free-air temperature ? c 430 420 410 400 ?75 0 25 50 440 450 chopping frequency vs free-air temperature 460 75 100 125 v dd = 5 v chopping frequency ? khz figure 17 |v dd | ? supply voltage ? v idd ? supply current ? ma i dd 1.2 0.8 0.4 0 023 5 1.6 supply current vs supply voltage 2 78 146 t a = 25 c t a = ? 55 c t a = 125 c v o = 0 no load ?50 ?25 t a ? free-air temperature ? c 1.2 0.8 0.4 0 ?75 0 50 1.6 supply current vs free-air temperature 2 100 125 25 75 v dd = 5 v v dd = 7.5 v v dd = 2.5 v v o = 0 no load idd ? supply current ? ma i dd figure 18 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 18 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 19 ?4 0 ?12 012345 ios ? short-circuit output current ? ma 4 8 short-circuit output current vs supply voltage 12 678 |v dd | ? supply voltage ? v i os v o = 0 t a = 25 c ?8 v id = ? 100 mv v id = 100 mv figure 20 ?50 ?25 0 ?10 ?15 ?75 0 25 50 5 10 short-circuit output current vs free-air temperature 15 75 100 125 t a ? free-air temperature ? c v id = 100 mv v id = ? 100 mv v dd = 5 v v o = 0 ios ? short-circuit output current ? ma i os ?5 figure 21 2 1 0 012 3 4 5 3 4 678 |v dd | ? supply voltage ? v slew rate vs supply voltage r l = 10 k ? c l = 100 pf t a = 25 c sr ? sr + sr ? slew rate ? v?us s v/ figure 22 ?50 ?25 2 1 0 ?75 0 25 50 sr ? slew rate ? v?us 3 slew rate vs free-air temperature 4 75 100 125 t a ? free-air temperature ? c s v/ v dd = 5 v r l = 10 k ? c l = 100 pf sr + sr ? ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 19 post office box 655303 ? dallas, texas 75265 typical characteristics figure 23 ?25 t ? time ? s vo ? output voltage ? mv 0 ?75 ?100 0123 25 75 voltage-follower small-signal pulse response 100 4567 50 v o v dd = 5 v r l = 10 k ? c l = 100 pf t a = 25 c ?50 figure 24 t ? time ? s vo ? output voltage ? v v o 0 ?1 ?3 ?4 0 5 10 15 20 1 3 voltage-follower large-signal pulse response 4 25 30 35 40 ?2 2 v dd = 5 v r l = 10 k ? c l = 100 pf t a = 25 c figure 25 f ch ? chopping frequency ? khz peak-to-peak input noise voltage vs chopping frequency 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 0246810 vn(pp) ? peak-to-peak input noise voltage ?uv n(pp) v v dd = 5 v r s = 20 ? f = 0 to 1 hz t a = 25 c v figure 26 f ch ? chopping frequency ? khz 3 2 1 0 0246 vn(pp) ? peak-to-peak input noise voltage ? uv 4 peak-to-peak input noise voltage vs chopping frequency 5 810 n(pp) v v dd = 5 v r s = 20 ? f = 0 to 10 hz t a = 25 c v
? slos019e ? september 1988 ? revised february 2005 20 post office box 655303 ? dallas, texas 75265 typical characteristics ? vn ? equivalent input noise voltage ? nv/hz 80 40 20 0 100 60 1 10 100 1 k f ? frequency ? hz equivalent input noise voltage vs frequency v n v dd = 5 v r s = 20 ? t a = 25 c nv/ hz figure 27 figure 28 |v cc | ? supply voltage ? v 1.9 1.8 012345 gain-bandwidth product ? mhz 2 gain-bandwidth product vs supply voltage 2.1 678 r l = 10 k ? c l = 100 pf t a = 25 c figure 29 ?50 t a ? free-air temperature ? c 2 1.8 1.4 1.2 ?75 0 25 50 gain-bandwidth product ? mhz 2.2 2.4 gain-bandwidth product vs free-air temperature 2.6 75 100 125 v dd = 5 v r l = 10 k ? c l = 100 pf ?25 figure 30 |v cc | ? supply voltage ? v om ? phase margin 023 5 phase margin vs supply voltage 78 146 r l = 10 k ? c l = 100 pf t a = 25 c m 50 48 46 44 42 40 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices.
? slos019e ? september 1988 ? revised february 2005 21 post office box 655303 ? dallas, texas 75265 typical characteristics ? figure 31 ?50 ?25 50 48 46 44 42 40 t a ? free-air temperature ? c ?75 0 50 phase margin vs free-air temperature 100 125 25 75 v dd = 5 v r l = 10 k ? c l = 100 pf om ? phase margin m figure 32 0 200 400 600 phase margin vs load capacitance 800 1000 v dd = 5 v r l = 10 k ? t a = 25 c c l ? load capacitance ? pf om ? phase margin m 60 50 40 30 20 10 0 ? data at high and low temperatures are applicable only within the rated operating free-air temperature ranges of the various dev ices. application information capacitor selection and placement the two important factors to consider when selecting external capacitors c xa and c xb are leakage and dielectric absorption. both factors can cause system degradation, negating the performance advantages realized by using the tlc2652. degradation from capacitor leakage becomes more apparent with the increasing temperatures. low-leakage capacitors and standoffs are recommended for operation at t a = 125 c. in addition, guard bands are recommended around the capacitor connections on both sides of the printed circuit board to alleviate problems caused by surface leakage on circuit boards. capacitors with high dielectric absorption tend to take several seconds to settle upon application of power, which directly affects input offset voltage. in applications where fast settling of input offset voltage is needed, it is recommended that high-quality film capacitors, such as mylar, polystyrene, or polypropylene, be used. in other applications, however, a ceramic or other low-grade capacitor can suffice. unlike many choppers available today, the tlc2652 is designed to function with values of c xa and c xb in the range of 0.1 f to 1 f without degradation to input offset voltage or input noise voltage. these capacitors should be located as close as possible to the c xa and c xb pins and returned to either v dd ? or c return. on many choppers, connecting these capacitors to v dd ? causes degradation in noise performance. this problem is eliminated on the tlc2652.
? slos019e ? september 1988 ? revised february 2005 22 post office box 655303 ? dallas, texas 75265 application information internal/external clock the tlc2652 has an internal clock that sets the chopping frequency to a nominal value of 450 hz. on 8-pin packages, the chopping frequency can only be controlled by the internal clock; however, on all 14-pin packages and the 20-pin fk package, the device chopping frequency can be set by the internal clock or controlled externally by use of the int/ext and clk in pins. to use the internal 450-hz clock, no connection is necessary. if external clocking is desired, connect int/ext to v dd ? and the external clock to clk in. the external clock trip point is 2.5 v above the negative rail; however, clk in can be driven from the negative rail to 5 v above the negative rail. if this level is exceeded, damage could occur to the device unless the current into clk in is limited to 5 ma. when operating in the single-supply configuration, this feature allows the tlc2652 to be driven directly by 5-v ttl and cmos logic. a divide-by- two frequency divider interfaces with clk in and sets the clock chopping frequency. the duty cycle of the external clock is not critical but should be kept between 30% and 60%. overload recovery/output clamp when large differential input voltage conditions are applied to the tlc2652, the nulling loop attempts to prevent the output from saturating by driving c xa and c xb to internally-clamped voltage levels. once the overdrive condition is removed, a period of time is required to allow the built-up charge to dissipate. this time period is defined as overload recovery time (see figure 33). typical overload recovery time for the tlc2652 is significantly faster than competitive products; however, if required, this time can be reduced further by use of internal clamp circuitry accessible through clamp if required. the clamp is a switch that is automatically activated when the output is approximately 1 v from either supply rail. when connected to the inverting input (in parallel with the closed-loop feedback resistor), the closed-loop gain is reduced, and the tlc2652 output is prevented from going into saturation. since the output must source or sink current through the switch (see figure 7), the maximum output voltage swing is slightly reduced. thermoelectric effects to take advantage of the extremely low offset voltage drift of the tlc2652, care must be taken to compensate for the thermoelectric effects present when two dissimilar metals are brought into contact with each other (such as device leads being soldered to a printed circuit board). dissimilar metal junctions can produce thermoelectric voltages in the range of several microvolts per degree celsius (orders of magnitude greater than the 0.01- v/ c typical of the tlc2652). to help minimize thermoelectric effects, careful attention should be paid to component selection and circuit-board layout. avoid the use of nonsoldered connections (such as sockets, relays, switches, etc.) in the input si gnal path. cancel thermoelectric ef fects by duplicating the number of components and junctions in each device input. the use of low-thermoelectric-coefficient components, such as wire-wound resistors, is also beneficial. 0 0 10203040 vi ? input voltage ? mv vo ? output voltage ? v t ? time ? ms 0 50 60 70 80 v i v o v dd = 5 v t a = 25 c figure 33. overload recovery ?5 ?50
? slos019e ? september 1988 ? revised february 2005 23 post office box 655303 ? dallas, texas 75265 application information latch-up avoidance because cmos devices are susceptible to latch-up due to their inherent parasitic thyristors, the tlc2652 inputs and output are designed to withstand ? 100-ma surge currents without sustaining latch-up; however, techniques to reduce the chance of latch-up should be used whenever possible. internal protection diodes should not, by design, be forward biased. applied input and output voltages should not exceed the supply voltage by more than 300 mv. care should be exercised when using capacitive coupling on pulse generators. supply transients should be shunted by the use of decoupling capacitors (0.1 f typical) located across the supply rails as close to the device as possible. the current path established if latch-up occurs is usually between the supply rails and is limited only by the impedance of the power supply and the forward resistance of the parasitic thyristor. the chance of latch-up occurring increases with increasing temperature and supply voltage. electrostatic discharge protection the tlc2652 incorporates internal esd-protection circuits that prevent functional failures at voltages at or below 2000 v. care should be exercised in handling these devices, as exposure to esd may result in degradation of the device parametric performance. theory of operation chopper-stabilized operational amplifiers of fer the best dc performance of any monolithic operational amplifier. this superior performance is the result of using two operational amplifiers, a main amplifier and a nulling amplifier, plus oscillator-controlled logic and two external capacitors to create a system that behaves as a single amplifier. with this approach, the tlc2652 achieves submicrovolt input offset voltage, submicrovolt noise voltage, and offset voltage variations with temperature in the nv/ c range. the tlc2652 on-chip control logic produces two dominant clock phases: a nulling phase and an amplifying phase. the term chopper-stabilized derives from the process of switching between these two clock phases. figure 34 shows a simplified block diagram of the tlc2652. switches a and b are make-before-break types. during the nulling phase, switch a is closed shorting the nulling amplifier inputs together and allowing the nulling amplifier to reduce its own input offset voltage by feeding its output signal back to an inverting input node. simultaneously, external capacitor c xa stores the nulling potential to allow the offset voltage of the amplifier to remain nulled during the amplifying phase. null amplifier in + in ? main amplifier v o v dd ? c xa c xb b a b a + + ? ? figure 34. tlc2652 simplified block diagram
? slos019e ? september 1988 ? revised february 2005 24 post office box 655303 ? dallas, texas 75265 application information theory of operation (continued) during the amplifying phase, switch b is closed connecting the output of the nulling amplifier to a noninverting input of the main amplifier. in this configuration, the input offset voltage of the main amplifier is nulled. also, external capacitor c xb stores the nulling potential to allow the offset voltage of the main amplifier to remain nulled during the next nulling phase. this continuous chopping process allows offset voltage nulling during variations in time and temperature over the common-mode input voltage range and power supply range. in addition, because the low-frequency signal path is through both the null and main amplifiers, extremely high gain is achieved. the low-frequency noise of a chopper amplifier depends on the magnitude of the component noise prior to chopping and the capability of the circuit to reduce this noise while chopping. the use of the advanced lincmos process, with its low-noise analog mos transistors and patent-pending input stage design, significantly reduces the input noise voltage. the primary source of nonideal operation in chopper-stabilized amplifiers is error charge from the switches. as charge imbalance accumulates on critical nodes, input offset voltage can increase, especially with increasing chopping frequency. this problem has been significantly reduced in the tlc2652 by use of a patent-pending compensation circuit and the advanced lincmos process. the tlc2652 incorporates a feed-forward design that ensures continuous frequency response. essentially, the gain magnitude of the nulling amplifier and compensation network crosses unity at the break frequency of the main amplifier. as a result, the high-frequency response of the system is the same as the frequency response of the main amplifier. this approach also ensures that the slewing characteristics remain the same during both the nulling and amplifying phases.
package option addendum www.ti.com 15-apr-2017 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples 5962-9089501mpa active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 9089501mpa tlc2652m 5962-9089503mca active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 5962-9089503mc a tlc2652amjb 5962-9089503mpa active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 9089503mpa tlc2652am tlc2652ac-14d active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ac tlc2652ac-8d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ac tlc2652ac-8dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ac tlc2652acn active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type tlc2652acn tlc2652acp active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ac tlc2652acpe4 active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ac tlc2652ai-14d active soic d 14 50 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ai tlc2652ai-8d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ai tlc2652ai-8dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ai tlc2652ai-8dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652ai tlc2652ai-8drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 85 2652ai tlc2652ain active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ain tlc2652aip active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ai
package option addendum www.ti.com 15-apr-2017 addendum-page 2 orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ball finish (6) msl peak temp (3) op temp (c) device marking (4/5) samples tlc2652aipe4 active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ai tlc2652amjb active cdip j 14 1 tbd a42 n / a for pkg type -55 to 125 5962-9089503mc a tlc2652amjb tlc2652amjg active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 tlc2652 amjg tlc2652amjgb active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 9089503mpa tlc2652am tlc2652c-8d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652c tlc2652c-8dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652c tlc2652c-8drg4 active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652c tlc2652cn active pdip n 14 25 pb-free (rohs) cu nipdau n / a for pkg type tlc2652cn tlc2652cp active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652cp tlc2652i-8d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652i tlc2652i-8dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652i tlc2652i-8dr active soic d 8 2500 green (rohs & no sb/br) cu nipdau level-1-260c-unlim 2652i tlc2652ip active pdip p 8 50 pb-free (rohs) cu nipdau n / a for pkg type tlc2652ip tlc2652m-8dg4 active soic d 8 1000 green (rohs & no sb/br) cu nipdau level-1-260c-unlim t2652m tlc2652mjg active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 tlc2652mjg tlc2652mjgb active cdip jg 8 1 tbd a42 n / a for pkg type -55 to 125 9089501mpa tlc2652m tlc2652q-8d active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim -40 to 125 t2652q tlc2652q-8dg4 active soic d 8 75 green (rohs & no sb/br) cu nipdau level-1-260c-unlim t2652q
package option addendum www.ti.com 15-apr-2017 addendum-page 3 (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. - the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. (4) there may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) multiple device markings will be inside parentheses. only one device marking contained in parentheses and separated by a "~" will appear on a device. if a line is indented then it is a continuation of the previous line and the two combined represent the entire device marking for that device. (6) lead/ball finish - orderable devices may have multiple material finish options. finish options are separated by a vertical ruled line. lead/ball finish values may wrap to two lines if the finish value exceeds the maximum column width. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis. other qualified versions of tlc2652, tlc2652a, tlc2652am, tlc2652m : ? catalog: tlc2652a , tlc2652 ? military: tlc2652m , tlc2652am
package option addendum www.ti.com 15-apr-2017 addendum-page 4 note: qualified version definitions: ? catalog - ti's standard catalog product ? military - qml certified for military and defense applications
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant tlc2652ai-8dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 tlc2652c-8dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 tlc2652i-8dr soic d 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 q1 package materials information www.ti.com 16-oct-2010 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) tlc2652ai-8dr soic d 8 2500 340.5 338.1 20.6 tlc2652c-8dr soic d 8 2500 340.5 338.1 20.6 tlc2652i-8dr soic d 8 2500 340.5 338.1 20.6 package materials information www.ti.com 16-oct-2010 pack materials-page 2
mechanical data mcer001a january 1995 revised january 1997 post office box 655303 ? dallas, texas 75265 jg (r-gdip-t8) ceramic dual-in-line 0.310 (7,87) 0.290 (7,37) 0.014 (0,36) 0.008 (0,20) seating plane 4040107/c 08/96 5 4 0.065 (1,65) 0.045 (1,14) 8 1 0.020 (0,51) min 0.400 (10,16) 0.355 (9,00) 0.015 (0,38) 0.023 (0,58) 0.063 (1,60) 0.015 (0,38) 0.200 (5,08) max 0.130 (3,30) min 0.245 (6,22) 0.280 (7,11) 0.100 (2,54) 0 15 notes: a. all linear dimensions are in inches (millimeters). b. this drawing is subject to change without notice. c. this package can be hermetically sealed with a ceramic lid using glass frit. d. index point is provided on cap for terminal identification. e. falls within mil std 1835 gdip1-t8

www.ti.com package outline c 14x .008-.014 [0.2-0.36] typ -15 0 at gage plane -.314.308 -7.977.83[ ] 14x -.026.014 -0.660.36[ ] 14x -.065.045 -1.651.15[ ] .2 max typ [5.08] .13 min typ [3.3] typ -.060.015 -1.520.38[ ] 4x .005 min [0.13] 12x .100 [2.54] .015 gage plane [0.38] a -.785.754 -19.94 19.15[ ] b -.283.245 -7.196.22[ ] cdip - 5.08 mm max height j0014a ceramic dual in line package 4214771/a 05/2017 notes: 1. all controlling linear dimensions are in inches. dimensions in brackets are in millimeters. any dimension in brackets or parenthesis are for reference only. dimensioning and tolerancing per asme y14.5m. 2. this drawing is subject to change without notice. 3. this package is hermitically sealed with a ceramic lid using glass frit. 4. index point is provided on cap for terminal identification only and on press ceramic glass frit seal only. 5. falls within mil-std-1835 and gdip1-t14. 7 8 14 1 pin 1 id (optional) scale 0.900 seating plane .010 [0.25] c a b
www.ti.com example board layout all around [0.05] max.002 .002 max [0.05] all around solder mask opening metal (.063) [1.6] (r.002 ) typ [0.05] 14x ( .039) [1] ( .063) [1.6] 12x (.100 ) [2.54] (.300 ) typ [7.62] cdip - 5.08 mm max height j0014a ceramic dual in line package 4214771/a 05/2017 land pattern example non-solder mask defined scale: 5x see detail a see detail b symm symm 1 7 8 14 detail a scale: 15x solder mask opening metal detail b 13x, scale: 15x

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